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? semiconductor msm6927/6947 1/31 ? semiconductor msm6927/6947 1200 bps single chip fsk modem general description the msm6927 and the msm6947 are oki's 1200 bps single chip modem series which transmit and receive serial, binary data over a switched telephone network using frequency shift keying(fsk). the msm6927 is compatible with itu-t v.23 series data sets, while the msm6947 is compatible with bell 202 series data sets. these devices provide all the necessary modulation, demodulation, and filtering required to implement a serial, asynchronous communication link. oki's single chip modem series is designed for users who are not telecommunication experts and are easy to use cost effective alternative to standard discrete modem design. cmos lsi technology provides the advantages of small size, low power, and increased reliability. the design of the integrated circuit assures compatibility with a broad base of installed low speed modems and acoustic couplers. applications include interactive terminals, desk top computers, point of sale equipment, and credit verification systems. features ? compatible with itu-t v.23 (msm6927) ? compatible with bell 202 (msm6947) ? cmos silicon gate process ? switched capacitor and advanced cmos analog technology ? data rate from 0 to 1200 bps ? half duplex (2-wire) ? receive squelch delay ? selectable built-in timers and external delay timers possible ? all filtering, modulation, demodulation, and dte interface on chip ? crystal controlled oscillator on chip ? ttl compatible digital interface ? low power dissipation: 90 mw typ. ? package options: 28-pin plastic dip (dip28-p-600C2.54) (product name: msm6927rs) (product name: msm6947rs) 44-pin plastic qfp (qfp44-p-910-0.80Ck) (product name: msm6927gs-k) (product name: msm6947gs-k) (qfp44-p-910-0.80C2k) (product name: MSM6927GS-2K) e2a0011-16-x1 this version: jan. 1998 previous version: nov. 1996
? semiconductor msm6927/6947 2/31 block diagram sg1 v a v d dg ain ft ao v a ag sg1 sg2 v ref x1 x2 clk ts1(msm6927rs)/ ts (msm6947rs) ts2(msm6927rs)/ ate (msm6947rs) ag sg2 cdr2 cdr1 rd1 rd2 cd2 rd rs1 rs2 cs cc lt cd1 xd carrier detect demodulator receive filter modulator transmit filter clock gen. osc sw rom cont. dte inter- face loop test delay sq
? semiconductor msm6927/6947 3/31 pin configuration (top view) ts2 (msm6927rs) ate (msm6947rs) 28 ts1 (msm6927rs) ts (msm6947rs) 27 v d 26 ao 25 v a 24 ft 23 sq 22 ain 21 sg1 20 ag 19 sg2 18 cdr2 17 cdr1 16 dg 15 x1 1 x2 2 clk 3 lt 4 cc 5 cs 6 rs1 7 rs2 8 xd 9 rd 10 cd1 11 cd2 12 rd1 13 rd2 14 28-pin plastic dip note: all pin descriptions except no. 27 pin and no. 28 pin are same for both msm6927rs and msm6947rs.
? semiconductor msm6927/6947 4/31 44-pin plastic qfp 11 10 9 8 7 6 5 4 3 2 1 23 24 25 26 27 28 29 30 31 32 33 ag sg1 nc ain nc nc nc nc sq ft v a nc rd xd rs2 nc nc nc rs1 cs cc nc 44 43 42 34 35 36 37 38 39 40 41 nc v d ao ts1 (msm6927gs-k) ts (msm6947gs-k) lt x2 x1 nc v a * ts2 (msm6927gs-k) ate (msm6947gs-k) clk 12 13 14 22 21 20 19 18 17 16 15 dg cdr2 sg2 cdr1 cd1 cd2 rd1 nc rd2 v a * nc notes: all pin description except no. 36 pin and no. 28 pin are same for both msm6927gs-k and msm6947gs-k. *: both no. 17 pin and no. 39 pin are set to be at v a level by setting no. 33 pin at v a level. nc: no connect pin
? semiconductor msm6927/6947 5/31 pin descriptions power dg 15 19 ground reference of v d (digital ground) ag 19 23 ground reference of v a (digital ground) v a 24 33 supply voltage (+12 v nominal) v d 26 35 supply voltage (+5 v nominal) name pin no. rs gs-k i/o description clocks x1 141 master clock timing is provided by either a series resonant crystal (3.579545 mhz 0.01%) connected across x1 and x2, or by an external ttl/cmos clock driving x2 with ac coupling. in this latter case, x1 is left unconnected. see fig. 10. x2 2 42 clk 343o 873.9 hz clock output. this clock is used to implement external delay circuits etc. name pin no. rs gs-k i/o description
? semiconductor msm6927/6947 6/31 control lt 444i digital loop back test. during digital "high", any data sent on the x d pin will appear on the rd pin, and any data sent on the rs1 pin will immediately appear on the cs pin. any data demodulated from the received carrier on the a in pin will be the modulated data to implement the transmitted carrier. in this case, sending the transmitted carrier to the phone line depends on the cc , but never on rs1 . during digital loop back test, the data on this pin becomes a control signal for sending the transmitted carrier to the phone line in place of rs1 . cc 52i when an external circuit gives the rs/cs delay time which is not within the device as required, this pin should be connected to the external circuit output. see fig. 11-1 or fig. 11-2 for msm6927, msm6947 respectively. rs2 88i the fast carrier detection output. this pin is internally connected to the input of the built-in carrier detect delay circuit. when an external delay circuit provides the delay time which is not within the device as required, the cd1 should be connected to the external circuit input. see fig. 11-1 or fig. 11-2 for msm6927, msm6947 respectively. cd1 11 12 o name pin no. rs gs-k i/o description cd2 12 13 i/o when an external circuit gives the carrier detect delay time which is not within the device as required, this pin becomes the input pin for the external circuit output signal. in other cases (when using the delay time within the device, the data on the ts1 (ts) or ts2 is not digital "high"), this pin becomes the carrier detect signal output. the rd1 data is demodulated data from the received carrier and the rd2 is the input of the following logic circuits referred to in fig. 12-1and fig. 12-2. for msm6927 and msm6947, respectively usually, the rd1 data is input directly to rd2. in some cases, as input data to rd2, the data that is controlled by ncu (network control unit) etc. may be required in stead of the rd1 data. rd1 13 14 o rd2 14 16 i these two pins are the output (crd1) and inverting input (cdr2) of the buffer operational amplifier of which the noninverting input is connected to the built-in voltage reference, stabilized to variations in the supply voltage and temperature. see fig. 13. an adequate carrier-detect level can be set by selecting the ratio of r 8 to r 9 . therefore, the loss in the received carrier level by phone-line transformer can be compensated by adjusting the ratio of r 8 to r 9 . r 8 + r 9 should be greater than 50 k w . cdr1 16 20 o cdr2 17 21 i when the data rate is 1200 bps and in half duplex mode on two-wire facilities, the delay function called as receiver-squelch is required. in case of four wire facilities, this function is not usually required. when a digital "high" is input to the sq pin, this function is omitted. sq 22 31 i this pin may be used for device tests only. during digital "high", the a o pin will be connected to receiving filter output instead of transmitting filter output. ft 23 32 i
? semiconductor msm6927/6947 7/31 both msm6927rs (or gs-k) and msm6947rs (or gs-k) have 28 (or 44) pins. the pin descriptions for these 28 (or 44) pins are same except those for no. 27 (or no. 36) pin and no. 28 (or no. 38). the pin descriptions for no. 27 (or no. 36) pin and no. 28 (or no. 38) pin are described as follows. msm6927 msm6947 name pin no. rs gs-k i/o description rs/cs delay and carrier detect delay options referred to chapter about timing characteristics are selected by ts1 and ts2 inputs. be careful that each delay can not be individually selected. if another delay time than the ones within the device are required as an option, input a digital "high" to the ts1 and ts2 pin and implement the external delay circuits to obtain the desired delay characteristics. in this case, the cd2 pin becomes not only the input for the external circuit output signal, but also the carrier detect output. see fig. 11-1. ts1 27 36 i ts2 28 38 i name pin no. rs gs-k i/o description when a digital "low" is input to the ts pin, the built-in rs/cs, carrier detect and receiver-squelch delay are provided. if another delay time is required, it can be implemented by inputting a digital "high" to this pin and incorporates the external delay circuits. in this case, the cd2 pin becomes not only the input for the external circuit output signal, but also the carrier detect output. see fig. 11-2. ts 27 36 i ate 28 38 i answer tone enable input. when a digital "low" is input to this pin and the rs1 pin is in the digital "low" level, the answer tone (to 2025 hz) is sent over the phone line via the a o pin.
? semiconductor msm6927/6947 8/31 input/output name pin no. rs gs-k i/o description cs 63o clear to send signal output. the digital "high" level indicates the "off" state and digital "low" indicates the "on" state. this output goes "low" at the end of a delay (rs/cs delay) initiated when rs1 (request to send) goes "low". request to send signal input. the digital "high" level indicates the "off" state. the digital "low" level indicates the "on" state and instructs the modem to enter the transmit mode. this input must remain "low" for the duration of data transmission. "high" turns the transmitter off. rs1 74i this is digital data to be modulated and transmitted via a o . digital "high" will be transmitted as "mark". digital "low" will be transmitted as "space". no signal appears at a o unless rs1 is "low". xd 99i digital data demodulated from a in is serially available at this output. digital "high" indicates "mark" and digital "low" indicates "space". for example, under the following condition, this output is forced to be "mark" state because the data may be invalid. ? when cd2 (carrier detect) is in the "off" state. ? when sq is in digital "low" (two-wire facilities) and rs1 is in the "on" state. ? during the receive data squelch delay at half duplex operation on two wire facilities. rd 10 10 o the sg1 and st2 are built-in analog signal grounds. sg2 is used only for carrier detect function. the dc voltage of sg1 is approximately 6 v, so the analog line interface must be implemented by ac coupling. see fig. 9. to make impedance lower and ensure the device performance, it is necessary to put bypass capacitors on sg1 and sg2 in close physical proximity to the device. sg2 18 22 o sg1 20 24 o this is the input for the analog signal from the phone line. the modem extracts the information in this modulated carrier and converts it into a serial data stream for presentation at rd output. a in 21 26 i this analog output is the modulated carrier to be conditioned and sent over the phone line. a o 25 34 o
? semiconductor msm6927/6947 9/31 absolute maximum ratings parameter power supply voltage symbol v a v d condition ta = 25c with respect to ag or dg rating C0.3 to 15 C0.3 to 7 unit v analog input voltage digital input voltage operating temperature storage temperature v ia v id t op t stg C0.3 to v a + 0.3 C0.3 to v d + 0.3 0 to +70 C55 to 150 c *1 *2 *1 *2 cdr2, a in x1, lt, cc , rs1 , rs2 , xd, cd2 , rd2, sq , ft, t s1 (ts), t s2 ( ate ) *3 *3 cd2 is i/o terminal
? semiconductor msm6927/6947 10/31 recommended operating conditions parameter unit max. typ. min. symbol condition power supply voltage v 13.2 12.0 10.8 va with respect to ag 5.25 5.00 4.75 vd with respect to dg 0 ag, dg operating temperature 70 0 t op c crystal 3.579545 mhz transformer impedance = 600 w r 1 600 w r 2 51 k w r 3 51 r 4 51 r 5 51 r 6 51 r 7 51 r 8 33 r 9 51 c 0 , c 1 0.047 c 2 2.2 c 3 22 c 4 0.01 c 5 10 c 6 10 m f a pp lication circuits usin g above conditions are p rovided in fi g . 8.
? semiconductor msm6927/6947 11/31 electrical characteristics dc and digital interface characteristics parameter unit max. typ. min. symbol condition power supply current ma 15.0 7.5 i a ordinary operation 2.0 1.0 i d 10 C10 i il v i = 0 v input leakage currnet 10 C10 i ih v i = v d m a input voltage 0.8 0 v il v (v a = 12 v 10%, v d = 5 v 5%, ta = 0 to 70c) *1 v d 2.2 v ih *1 output voltage 0.4 0 v ol i ol = 1.6 ma v d 0.8 vd v oh i oh = 400 m a *2 *1 lt, cc , rs1 , rs2 , xd, cd2 , rd2, sq , ft, t s1 (ts), t s2 ( ate ) *2 clk, cs , rd, cd1 , cd2 , rd1 *3 *3 *3 cd2 is i/o terminal.
? semiconductor msm6927/6947 12/31 analog interface characteristics 1. msm6927 transmit carrier out (a o ) parameter unit max. typ. min. symbol condition carrier frequency hz 1310 1300 1290 f m f crystal = 3.579545 mhz (v a = 12 v 10%, v d = 5 v 5%, ta = 0 to 70c) mark 1 2100 2100 2090 f s space 0 output resistance 200 r oxa w load resistance 50 r lxa k w load capacitance 100 c lxa pf transmit level 8 6 4 v oxa *1 dbm output offset voltage v a 2 v osx v C1 v a 2 v a 2 + 1 c 1 = 0.047 m f out-of-band energy (referred to carrier level) refer to fig. 1 e ox db receive carrier input (a in ) parameter unit max. typ. min. symbol condition input resistance k w 100 r ira receive signal level range *1 dbm C6 C48 v ira carrier detect level C43 v cd on r 8 = 33 k w r 9 = 51 k w C48 v cd off on off *2 carrier detect hysteresis db 2 h ys v cd on C v cd off receive filter parameter unit max. typ. min. symbol condition group delay distortion m s 210 d dl 1100 to 2300 hz notes: *1 0 dbm = 0.775 vrms *2 the resistor values are typical
? semiconductor msm6927/6947 13/31 figure 1 msm6927 out-of-band energy referred to carrier level (c 1 = 0.047 m f) khz 0 C20 C40 C60 0246810121416 db
? semiconductor msm6927/6947 14/31 0 C1 1 k freq (hz) gain (db) 10 k C2 C3 C10 C20 C30 C80 C70 C60 C50 C40 C30 C20 gain (db) figure 2 msm6927 transmit filter 1 k freq (hz) 10 k 0 C10 C20 C30 C40 C50 C60 gain (db) figure 3 msm6927 receive filter
? semiconductor msm6927/6947 15/31 2. msm6947 transmit carrier out (a o ) receive carrier input (a in ) parameter unit max. typ. min. symbol condition input resistance k w 100 r ira receive signal level range *1 dbm C6 C48 v ira carrier detect level C43 v cd on r 8 = 33 k w r 9 = 51 k w C48 v cd off on off *2 carrier detect hysteresis db 0.5 h ys v cd on C v cd off receive filter parameter unit max. typ. min. symbol condition group delay distortion m s 210 d dl 1100 to 2300 hz notes: *1 0 dbm = 0.775 vrms *2 the resistor values are typical parameter unit max. typ. min. symbol condition carrier frequency hz 1210 1200 1190 f m f crystal = 3.579545 mhz (v a = 12 v 10%, v d = 5 v 5%, ta = 0 to 70c) mark 1 2210 2200 2190 f s space 0 answer tone frequency 2031 2025 2019 f a output resistance 200 r oxa w load resistance 50 r lxa k w load capacitance 100 c lxa pf transmit level 8 6 4 v oxa *1 dbm output offset voltage v a 2 v osx v C1 v a 2 v a 2 + 1 c 1 = 0.047 m f out-of-band energy (referred to carrier level) refer to fig. 4 e ox db ate = "0"
? semiconductor msm6927/6947 16/31 figure 4 msm6947 out-of-band energy referred to carrier level (c 1 = 0.047 m f) khz 0 C20 C40 C60 0246810121416 db 200 C25 C55 3.4 15 db/octave
? semiconductor msm6927/6947 17/31 0 C1 1 k freq (hz) gain (db) 10 k C2 C3 C10 C20 C30 C80 C70 C60 C50 C40 C30 C20 gain (db) figure 5 msm6947 transmit filter 1 k freq (hz) 10 k 0 C10 C20 C30 C40 C50 C60 gain (db) figure 6 msm6947 receive filter
? semiconductor msm6927/6947 18/31 demodulated bit characteristics timing characteristics 1. msm6927 parameter unit max. typ. min. symbol condition rs/cs delay time ms 205 200 195 t rc on rs1 = "0" ? cs = "0" (v a = 12 v 10%, v d = 5 v 5%, ta = 0 to 70c) ts1 ts2 00 35 30 25 01 75 70 65 10 external delay timer 11 rs1 = "1" ? cs = "1" t rc off 0.5 0 ** 25 10 00 25 10 01 25 10 10 external delay timer 11 cd/on delay time t cd on 15 5 00 15 5 01 15 5 10 external delay timer 11 cd/off delay time t cd of soft turn-off time t st ** 10 155 150 145 00 155 150 145 01 45 40 35 10 external delay timer receive data squelch delay time t sq sq = "0" 11 rs1 = "1" ? rd = "1" hold parameter unit max. typ. min. symbol condition peak intersymbol distortion % 9 id back-to-back over input signal range C6 to C40 dbm. 511-bit test pattern. (v a = 12 v 10%, v d = 5 v 5%, ta = 0 to 70c) 8 db 11 db s/n back-to-backwith 0.3 to 3.4 khz flat noise. receive signal level C25 dbm. 511-bit test pattern bit error rate 10 C3 ber 10 C5 refer to fig. 7 notes: *: irrespective of i/o condition
? semiconductor msm6927/6947 19/31 2. msm6947 parameter unit max. typ. min. symbol condition rs/cs delay time ms 185 180 175 t rc on rs1 = "0" ? cs = "0" (v a = 12 v 10%, v d = 5 v 5%, ta = 0 to 70c) ts 0 external delay timer 1 rs1 = "1" ? cs = "1" t rc off 0.5 0 * 35 15 0 external delay timer 1 cd/on delay time t cd on 20 10 0 external delay timer 1 cd/off delay time t cd of soft turn-off time t st * 10 156 0 external delay timer 1 receive data squelch delay time t sq sq = "0" rs1 = "1" ? rd = "1" hold refer to fig. 8 notes: *: irrespective of i/o condition +: reserved
? semiconductor msm6927/6947 20/31 timing diagram rs1 cs ao t rcon t rcoff t st t cdon t cdoff cd2 ain t sq "mark" hold figure 7 msm6927/6947 timing diagram
? semiconductor msm6927/6947 21/31 application circuit 1. msm6927rs notes: 1. the crystal should be wired in close physical proximity to the device. 2. high level signals should not be routed next to low level signals. 3. bypass capacitors on v a , sg1, and sg2 should be as close to the device as possible. 4. ag and dg should be connected as close to the system ground as possible. figure 8-1 application circuit using msm6927rs clk x 2 x 1 cc cs rs1 rs2 rd phone line crystal lt xd cd1 cd2 rd1 rd2 dg 28 27 26 25 24 23 22 21 20 19 18 17 16 15 v d ts 1 ts 2 v a ft sq ain ag ao sg1 sg2 cdr2 cdr1 dg ag v a v d c6 + 4-wire 2-wire test data control cs rs rd xd cd v d c5 r 4 r 6 r 7 r 5 c0 r 2 r 3 + C r 1 c3 c4 r 8 r 9 dg or v d v d c2 c1 C 1 2 3 4 5 6 7 8 9 10 11 12 13 14 C + + C
? semiconductor msm6927/6947 22/31 2. msm6947rs notes: 1. the crystal should be wired in close physical proximity to the device. 2. high level signals should not be routed next to low level signals. 3. bypass capacitors on v a , sg1, and sg2 should be as close to the device as possible. 4. ag and dg should be connected as close to the system ground as possible. figure 8-2 application circuit using msm6947rs clk x 2 x 1 cc cs rs1 rs2 rd phone line crystal lt xd cd1 cd2 rd1 rd2 dg 28 27 26 25 24 23 22 21 20 19 18 17 16 15 v d ts ate v a ft sq ain ag ao sg1 sg2 cdr2 cdr1 dg ag v a v d c6 + 4-wire 2-wire test data control cs rs rd xd cd v d c5 r 4 r 6 r 7 r 5 c0 r 2 r 3 + C r 1 c3 c4 r 8 r 9 dg or v d v d c2 c1 C 1 2 3 4 5 6 7 8 9 10 11 12 13 14 C + + C v d data ans. tone
? semiconductor msm6927/6947 23/31 25 20 21 19 sg1 ain ao ag r 4 r 6 r 7 r 5 c 0 + C r 2 r 3 + C r 1 c2 c1 600 w : 600 w c3 +6 dbm 0 dbm C6 dbm 0 dbm C6 dbm phone line figure 9 msm6927rs/msm6947rs application note: the signal level on the a in pin should not exceed C6 dbm. c 0 , c 1 c 2 c 3 r 1 0.047 m f 2.2 m f 1 m f 600 w r 2 r 3 r 4 r 5 51 k w 51 k w 51 k w (51 k w ) transmit signal level r 6 r 7 r 8 r 9 (51 k w ) receive signal level 51 k w (33 k w ) carrier detect level 51 k w x2 x1 external oscillator *1 *2 external oscillator connection *1 *2 ttl or hi-speed cmos gate left unconnected 200 pf v d 3.58 mhz gate figure 10
? semiconductor msm6927/6947 24/31 rck 4020 *1 (c) rck 4020 *1 (d) rck 4020 *1 (a) v d v d rs ck q q d 873.9 hz cd1 rs1 cd2 clk ts2 rs2 ts1 rck 4020 *1 (b) cd *2 *2 (a) rs/cs delay, (b) receive-squelch delay, (c) cd/on delay, (d) cd/off delay note: supply voltage equals v d for all gates. *1: the desired delay can be realized by selecting the appropriate bits from 4020's outputs. the number of the bits is not always 3. each delay can be set differently from built-in delays. *2: in case that the receiver-squelch delay is unnecessary, circuit (b) and this or gate should be omitted and the output of the nor gate should be connected to cd2 directly. figure 11-1 msm6927 external delay connection
? semiconductor msm6927/6947 25/31 (a) rs/cs delay, (b) receive-squelch delay, (c) cd/on delay, (d) cd/off delay note: supply voltage equals v d for all gates. *1: the desired delay can be realized by selecting the appropriate bits from 4020's outputs. the number of the bits is not always 3. each delay can be set differently from built-in delays. *2: in case that the receiver-squelch delay is unnecessary, circuit (b) and this or gate should be omitted and the output of the nor gate should be connected to cd2 directly. figure 11-2 msm6947 external delay connection rck 4020 *1 (c) rck 4020 *1 (d) rck 4020 *1 (a) v d v d rs ck q q d 873.9 hz cd1 rs1 cd2 clk ts2 rs2 ts1 rck 4020 *1 (b) cd *2 *2
? semiconductor msm6927/6947 26/31 ts1 ts2 sw control lt rs/cs delay modulator transmit filter de- modulator receive filter carrier detect rs1 cs rs2 cc xd rd cd2 cd1 rd2 rd1 ao ain sq delay cd on cd off squelch rd squelch delay figure 12-1 msm6927 equivalent logic interface of the integrated modem
? semiconductor msm6927/6947 27/31 figure 12-2 msm6947 equivalent logic interface of the integrated modem ts1 ts2 sw control lt rs/cs delay modulator transmit filter de- modulator receive filter carrier detect rs1 cs rs2 cc xd rd cd2 cd1 rd2 rd1 ao ain sq delay cd on cd off squelch rd squelch delay
? semiconductor msm6927/6947 28/31 figure 13 external resistor connection for the setting of carrier detect level r 9 cd1 cdr1 cdr2 r 8 sg2 carrier detect ac/dc converter carrier sg2 v ref comp + C (r8 + r9) 3 50 k w
? semiconductor msm6927/6947 29/31 (unit : mm) package dimensions dip28-p-600-2.54 package material lead frame material pin treatment solder plate thickness package weight (g) epoxy resin 42 alloy solder plating 5 m m or more 4.30 typ.
? semiconductor msm6927/6947 30/31 (unit : mm) notes for mounting the surface mount type package the sop, qfp, tsop, soj, qfj (plcc), shp and bga are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. therefore, before you perform reflow mounting, contact okis responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). qfp44-p-910-0.80-k package material lead frame material pin treatment solder plate thickness package weight (g) epoxy resin 42 alloy solder plating 5 m m or more 0.35 typ. mirror finish
? semiconductor msm6927/6947 31/31 (unit : mm) notes for mounting the surface mount type package the sop, qfp, tsop, soj, qfj (plcc), shp and bga are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. therefore, before you perform reflow mounting, contact okis responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). package material lead frame material pin treatment solder plate thickness package weight (g) epoxy resin 42 alloy solder plating 5 m m or more 0.41 typ. qfp44-p-910-0.80-2k mirror finish

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